An extensively used bi-directional signal transmission system is the Inter Integrated Circuit Bus system (I2C Bus system), disclosed in the Philips Data Handbook IC12a, 1989, and “The I2C Bus and how to use it (including specifications)” 1995 Philips Semiconductors.
The I2C Bus system, is a serial bus system for communication of data between individual integrated circuits, or stations, that are interconnected through a bi-directional two wire transmission channel. Of the two wires, one carries a clock signal, and the other the data, with a predetermined communication protocol. Depending on the particular function within the system, an individual station can act as a transmitter, or as a receiver.
The I2C Bus was developed to allow communication of data between integrated circuits on a single assembled printed circuit board in a manner which does not require either a wide communication bus or individual address lines between ICs (integrated circuits) in order to achieve that communication. For example, in the absence of such a bus in a digital voltmeter, the communication between the parts of the circuit performing range switching, the measuring circuit, the controller, the measurement memory, and the display drive can be designed with multiple wire parallel buses between each integrated circuit used to construct the meter. This presents a challenge to design an efficient printed circuit layout with so many interconnections on the circuit board. Much of the complexity is because it requires parallel bus pins on each IC to accommodate all of these interconnections.
In the digital voltmeter example, and in many other devices, the communication between each block in the circuit does not need high speed communication in real time, and the two wire I2C bus offers an opportunity of providing all of the data communication with only the two bus Wires which make up the common bus connected to each I2C enabled IC in turn in the system.
The advantages offered by the I2C Bus were evident from its inception. However, the specification is somewhat limiting. There have been numerous efforts to expand its application. The most important limitation which has been sought to be overcome is the distance over which the bus can operate. For use between different printed circuit boards, or between adjacent racks of equipment, between rooms, or between separate buildings it becomes impossible to continue to comply with the I2C bus rules for maximum capacitance on the communication lines. Designers also wanted to be able to connect greater numbers of I2C Bus ICs than were permitted by the I2C Bus Design Rules. A further problem was found where I2C devices needed to communicate but were operating from different power supply voltages.
There are also other bus communication interfaces in which problems are overcome by having the forward signal path split from the reverse signal (avoiding the design difficulties inherent in a single bus path being used for bi-directional communication, and offering the possibility of opto-isolation, or complementary pair transmission protocols and other circuits to overcome common mode interference) that were not able to be used or interfaced with I2C or other bi-directional systems.
In the I2C Bus system the two wires are the data wire (SDA) and the clock wire (SCL). In operation both are connected to a positive supply (VCC) through pull-up resistors. When the stations are not communicating the clock and data lines are free, and pulled high by these resistors. Each station which can communicate on the bus has an open collector or open drain output which can pull down the bus lines to a voltage level close to the negative supply (VEE).
The I2C Bus protocol has been defined so that two or more ICs may start to transmit at the same time, with all ICs connected to the bus monitoring the bus line voltage, including the two or more which have started transmitting. As soon as one of those transmitting ICs detects that the bus has remained LOW even when that IC is attempting to transmit a HIGH signal, then that IC will immediately stop transmitting. That is when it detects the LOW being transmitted by another IC, when it was attempting to send a HIGH it stops transmitting and waits to retry at a later opportunity when hopefully there will be no contention.
The distance over which the bus can communicate, and the number of stations allowed is determined by the load presented on the bus line by its total capacitive load. That is by the total of the capacitance of the bus wiring, the connections, the IC pins, and the capacitive load of the input/output circuit of each IC, if the bus capacitance is increased then the maximum possible speed of the bus is limited, and the slower rise and fall times on the bus start to cause difficulties.
A number of design suggestions have been made to overcome these problems of expanding and extending the application of the I2C Bus. Many simple circuits have been published seeking to provide this expanded capability. Most of these circuits have problems which may be associated with latching, be only conditionally stable, or present glitches, and not be able to reverse their direction of signal flow when active. For example a circuit will latch if when the receiving logic path goes low, and when it transfers this input low to its output, the output in turn is detected as being low, and this low signal is returned to the input as a low signal, holding the original input low, even when the original external low drive signal is removed. Thus the bus has ‘latched’ into this low state.
Many circuits have been suggested that fail to buffer the signals properly. If one side is held low, and while still low its output is held low, and then the original input drive is released, the application of the low on the output side should continue to hold the input bus low. Unfortunately many proposed circuits fall this test, and the input goes high for the time needed for the buffer circuit to recognise that the signal path has reversed, generating a short pulse or glitch on the input. Let us call this the glitch test.
The problem arises during the sort of pulse sequence which might occur during bus arbitration. In this test when the input to the bus is pulled LOW, the output side of the buffer circuit follows and goes LOW. If the output is then held LOW by another IC pulling it LOW on the output side (noting that it is already LOW at that time, being held LOW by the original input signal being LOW and acting via the forward path through the buffer) then that output will be held LOW by both the input LOW, and the output being held LOW on that side externally. If the input LOW is then released, and we watch the voltage on the input side, observing the behaviour of the input pin voltage after it is released, we ought to observe that it remains LOW because the output is being held LOW. However in many of these buffer circuits the forward path from input to output is active (and not the reverse path) only until after the input LOW is released. To prevent latching this active path has locked out the reverse path from output back to the input side of the buffer. But when the input drive holding the input LOW is released, the input pin will initially go HIGH to turn off the forward signal path, and only after the time delay needed for this signal to propagate to the output, will the externally applied LOW on the output be able to be detected, and the reverse path from output to input enabled, finally, after a further propagation delay pulling the input pin LOW again to reflect the LOW at the output pin. This HIGH on the input pin which appears when the pin is released in this test, appears as a HIGH pulse or glitch until the LOW signal from the output is propagated back to the input and able to pull it low. This glitch can present a HIGH signal to the ICs on the bus at a time when the bus should be held LOW without a glitch.
A buffer circuit has been described in U.S. Pat. No. 5,790,526, Bi-Directional Signal Transmission System and Adapter for such a system. In this patent an I2C Bus buffer is described in which the input and output are connected through a low impedance resistor, and the voltage generated by the current flowing in this resistor is used to boost the pull-down capability on the bus. An integrated circuit based on this invention is the P82B715 Bus Buffer, distributed by Philips. This IC provides a boosted bus drive on the bus output, offering an increase in pull down drive capability of 10 times the normal I2C Bus pull down capability. This increased pull-down capability is equivalent to a lowering of the bus impedance, and therefore an ability to drive a 10 times increased capacitive load. This device passes the glitch test and offers an expansion capability by allowing a load to be driven which presents an increased capacitance on the buffered bus side. It does not allow interfacing of stations with different supply voltages. However the P82B715 also has a fairly large power supply current demand of 15 mA typical, making it difficult to use in applications where the available power supply current is limited.
Another circuit is described in U.S. Pat. No. 6,014,040, Bi-Directional Signal Transmission System. In this circuit, which has been realised in the integrated circuit P82B96, distributed by Philips, the loop between the forward and the reverse buffered signal has been broken by adopting two voltage levels on the input side, the lower of which corresponds to the input being held low, and therefore activating the forward signal path, and a slightly higher voltage (still able to be interpreted by ICs (stations) connected on the input side as a bus low signal) which is the low output of the reverse path, but is not sufficiently low to activate the forward path input comparator. The P82B96 offers split input and output on the output bus side so that it can be interfaced to other ICs in which the transmit and receive path are separate. If this capability is not needed then the bus out, and bus receive pins may be Wired together to give a single output buffer.
The first example of these two buffers offers only forward current gain, and no voltage gain. Therefore it is stable, and does not latch or oscillate. The P82B96 breaks the loop of the forward and reverse paths by using a lower input voltage threshold in the forward path avoiding latching and instability. It also has the backward signal path active when the input is held low, and therefore does not generate a glitch it the low is switched from input to output while active low. As the two voltage thresholds are set internally in the integrated circuit, and are chosen to be consistent with the thresholds defined in the I2C standards when run from a 5 volt supply, difficulties have arisen since it was first designed as the power supply voltages for ICs have been reduced to take advantage of lower power and higher speeds. While the P82B96 has been designed to operate with a supply of less than 2 volts, the voltage of 0.8 volts which corresponds to a low being received on the bus output (that is when the low on the output pin means that the reverse path is active, and is setting the input voltage to low) can be too high to interface with ICs designed for such low supply voltages. This voltage may be higher than the low threshold that is detected by a low voltage I2C device which is connected to the input bus. In this way there are design problems in using the P82B96 at low voltages because these input threshold voltages are fixed internally.
However one advantage of the P82B96 derives from it offering true buffering between the input and the output side. Thus circuitry connected to the output does not add any more to the capacitive load on the input I2C Bus. In addition the output is capable of higher current drive than allowed by the I2C standard (the limit on the input side), and further P82B96 devices can be connected elsewhere on the output bus, to offer other I2C compatible parts of the network on their inputs. Thus the P82B96 can permit buffers to be connected in series, expanding and extending the network beyond the maximum capactive load limit that would make it unworkable if no buffer is used.
Other advantages of the P82B96 include the ability of the output being split into transmit and receive paths thus allowing opto-couplers to electrically isolate two sides of the bus. With such isolation power supplies can be used which reference different ground (common) systems on each side of the opto-isolation. With external circuitry, the VCC supply can be switched off, allowing both the input and output buses to operate without interconnection and interaction. This can be important in cases where part of the bus may be driven from a power supply which can be switched off, or becomes isolated under fault conditions. In most ICs the bus is shorted when the power supply fails.
Another bus buffer is the Linear Technology Hot Swappable 2-Wire Bus buffer, the LTC4300-1 and LTC4300-2. These buffers allow Input/Output card insertion into a live backplane without corruption of the clock and data busses. It employs rise-time accelerator circuitry that is described in U.S. Pat. No. 6,650,174, and uses this facility to allow the use of weaker DC pull-up currents while still meeting the rise-time specifications of the I2C standard. Weaker pull up currents which are achieved by increasing the resistance of the pull-up resistors on the bus, offer a saving in DC power supply current and enable operation at lower pull down currents. However this has moved away from the common standard of the I2C range of devices which all have a standard pull-down capability of 3 mA.
The LTC4300-1 and LTC4300-2 have a maximum voltage drop of 0.4 volts between input and output when sinking 3 mA, This prevents two such devices operating in series if they are being used with 3 mA pull-down current.
Objects and advantages of the present invention will become apparent from the following description, taken in connection with the accompanying drawings, wherein, by way of illustration and example, an embodiment of the present invention is disclosed